Descripción de la oferta
At LuxQuanta, we are pioneering the Quantum Communications industry by delivering solutions that use the properties of quantum physics to secure communications. As we spearhead our international expansion after our first three years of solid growth, we invite passionate individuals to join us on our journey. We expect you to help us continue leading the fast‑paced market of Quantum Communications in Europe and beyond.Inscríbase (haciendo clic en el botón correspondiente) después de revisar toda la información relacionada con el trabajo a continuación.About the roleThe ideal candidate will be responsible for maintaining the RTL codebase and low‑level Python/Rust firmware, as well as taking ownership of CI/CD pipelines for testing, synthesis, and implementation.He/she will gain deep knowledge of the underlying DSP and gateware/firmware interfaces and will eventually take responsibility for the continuous improvement of the FPGA logic that orchestrates our commercial CV‑QKD products.Tasks & ResponsibilitiesUnderstand the DSP and RTL architecture of the CV‑QKD transceiverDesign and maintain CI/CD pipelines for RTL unit testing, system‑level testing, and bitstream generationCollaborate with the firmware team to strengthen the security and resilience of Python and Rust driversSupport the production and testing teams in identifying and resolving bottlenecks and failures for upcoming FPGA image and driver releasesAssist the production and testing teams in evaluating and integrating new opto‑electronic componentsPerform hands‑on testing and verification on dedicated CV‑QKD transceivers at LuxQuanta’s facilities, when requiredQualifications / ExperienceDegree in Electronics Engineering, Electrical Engineering, Physics, Telecommunications, or a related field4+ years of experience in FPGA programming in an industrial or production environmentProgramming languages: Verilog, Python, C, TCL (Rust is a plus)Proficiency in developing and testing RTL code for AMD/Xilinx FPGAs, including AXI‑4 interfaces, IP packaging flows, and timing closure analysisExperience developing low‑level driver code (Python, C, or Rust) to control RTL logic and external peripherals via SPI/I2CExperience designing and maintaining CI/CD pipelines and using external testing/build agents for RTL testing and bitstream generationProficient with Git and standard version control workflowsBasic electronics knowledge, including the ability to read schematics and datasheetsStrong collaboration skills and the ability to work closely with firmware and hardware engineers during system designExperience with Zynq / Zynq UltraScale+ FPGA architectures is a plusExperience with embedded build environments (e.g., Buildroot, Yocto, Petalinux) is a plusCompensationCompetitive salary, private health insurance and ticket guarderia.Lunch at the office for less than 2€!Flexible working hours and hybrid work model.Short Fridays during the Summer. xcskxlj Opportunities for professional development and career growth in a vibrant multicultural work environment in Barcelona.#J-18808-Ljbffr
