Descripción de la oferta
Senior FPGA Developer – Barcelona (Hybrid Contract Role)Drive hands-on FPGA development for a commercial synchronisation platform powering quantum computing, 6G communications, and next-generation measurement systems.We're hiring a Senior FPGA Developer to join an international R&D team in Barcelona working on a high-precision synchronisation solution used in advanced research and emerging technologies worldwide.This is a hands-on senior role where you will: ✔ Implement and extend a proven FPGA architecture ✔ Drive delivery across complex timing and synchronisation systems ✔ Collaborate closely with architects and developers across global engineering teamsContract StructureInitial 6-month contract (ASAP start), with a high expectation of extension to 12 months and beyond as the project roadmap develops.The RoleYou'll be an active contributor within an established architecture — taking ownership of implementation, extending product capabilities, and ensuring technical quality across a commercially deployed synchronisation platform.What You'll Do Hands-On FPGA DevelopmentDrive SystemVerilog-based implementation to extend and enhance the existing platform, delivering new features for next-generation timing and synchronisation applications.Technical CollaborationWork closely with the Product Owner, architects, and developers across multiple projects and distributed teams to align on implementation, integration, and product direction.Validation & QualityContribute to FPGA validation, simulation, and static timing analysis, maintaining the rigour and reliability the product demands.Stakeholder EngagementParticipate in technical discussions, contribute to cross-functional decision-making, and translate partner needs into well-integrated FPGA solutions.✅What We're Looking For BS/MS/PhD in Electrical Engineering or Computer Science (FPGA focus preferred) 7+ years in digital electronics with a strong hands-on FPGA development background Strong SystemVerilog expertise Solid experience in FPGA validation, simulation, and static timing analysis Familiarity with Xilinx devices and the Vivado toolchain Good understanding of FPGA block and IP core integration within complex systems Ability to work effectively within an existing architecture and contribute to its evolution
