Descripción de la oferta
Senior Layout Engineer page is loaded## Senior Layout Engineerlocations:Siga leyendo para descubrir lo que necesitará para tener éxito en este puesto, incluyendo habilidades, cualificaciones y experiencia.Spain, Valencia, Cortes Valencianastime type:Full timeposted on:Posted Todayjob requisition id:R255686**About Analog Devices**Analog Devices, Inc. (NASDAQ:) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more atand onand .Position OverviewAs ADI expands into new product and market segments, the Micro Electro-Mechanical Systems Technology Group (MEMS TG) is seeking a Senior Layout Engineer based in Valencia. This role is ideal for an experienced engineer ready to take on more complex design challenges, mentor junior team members, and contribute to cross-site projects with global impact.Join our world-class MEMS team in Valencia and help drive technical excellence and innovation.The RoleAs a Senior Layout Engineer, you will:\* Lead and execute complex block and top-level layouts for Mixed-Signal/Analog circuits in 180nm and 40nm CMOS and DMOS technologies.\* Collaborate closely with design, verification, and packaging teams across multiple sites.\* Drive layout reviews and provide technical guidance to less experienced engineers.\* Optimize layouts for performance, manufacturability, and reliability, with a strong focus on matching, symmetry, and parasitic minimization.\* Develop and document best practices, methodologies, and layout flows.\* Support package design integration as needed.Requirements\* BSEE degree or equivalent and 4+ years of proven experience in Mixed-Signal/Analog full custom layout IC, including hands-on experience with 180nm and 40nm CMOS and DMOS technologies.\* Deep knowledge of device physics, semiconductor processing, and advanced layout techniques.\* Proficiency in tools such as Cadence Virtuoso and Calibre.\* Demonstrated ability to lead layout projects and mentor junior engineers.\* Strong problem-solving, organizational, and communication skills.\* Self-driven, detail-oriented, and committed to continuous improvement.\* Collaborative mindset and ability to work effectively in a global team.\* High tolerance for ambiguity and a passion for innovation.Why you will like working at ADI\* Opportunity to lead challenging projects and influence technical direction.\* Freedom to explore new ideas and drive process improvements.\* Emphasis on professional development, mentoring, and career growth.\* A culture that values individual judgment and aligns personal and company goals.*For positions requiring access to technical data, Analog Devices, Inc. may have to obtain exportlicensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.**Analog Devices is an equal opportunity employer. xcskxlj We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.*Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days#J-18808-Ljbffr
